Title:
【発明の名称】調整されていないアクセスをサポートするメモリデバイス
Document Type and Number:
Japanese Patent JP2003523598
Kind Code:
A
Abstract:
An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided. The enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.
Inventors:
Oberlaender, Claus
Landawa, Sabine
Les Arts, Vincent
Fleck, Rod G.
Landawa, Sabine
Les Arts, Vincent
Fleck, Rod G.
Application Number:
JP2001560405A
Publication Date:
August 05, 2003
Filing Date:
January 22, 2001
Export Citation:
Assignee:
Infineon Technologies North America Corporation
International Classes:
G11C7/10; G11C8/10; G11C8/12; G11C11/417; G11C11/41; G11C11/418; (IPC1-7): G11C11/417; G11C11/41; G11C11/418
Attorney, Agent or Firm:
Shusaku Yamamoto (2 outside)