Title:
高速メモリーバス上の同期データ書込み
Document Type and Number:
Japanese Patent JP2004507032
Kind Code:
A
Abstract:
Some synchronous semiconductor memory devices accept a command clock which is buffered and a write clock which is unbuffered. Write command are synchronized to the command clock while the associated write data is synchronized to the write clock. Due to the use of the buffer, an arbitrary phase shift can exist between the command and write clocks. The presence of the phase shift between the two clocks makes it difficult to determine when a memory device should accept write data associated a write command. A synchronous memory device in accordance with the present invention utilizes the unbuffered strobe signal which is normally tristated during writes as a flag to mark the start of write data. A preamble signal may be asserted on the strobe signal line prior to asserting the flag signal in order to simplify flag detection.
Inventors:
Brent Keith
Brian johnson
Brian johnson
Application Number:
JP2002521301A
Publication Date:
March 04, 2004
Filing Date:
August 21, 2001
Export Citation:
Assignee:
MICRON TECHNOLOGY, INC.
International Classes:
G11C11/407; G06F12/00; G06F13/16; G11C7/10; G11C7/22; G11C11/4076; (IPC1-7): G11C11/407
Domestic Patent References:
| JPH10228774A | 1998-08-25 | |||
| JP2003228511A | 2003-08-15 | |||
| JP2003167778A | 2003-06-13 | |||
| JP2000011646A | 2000-01-14 | |||
| JPH1028041A | 1998-01-27 | |||
| JPH11163259A | 1999-06-18 | |||
| JP2000163308A | 2000-06-16 | |||
| JP2003228511A | 2003-08-15 | |||
| JP2003167778A | 2003-06-13 |
Foreign References:
| WO1998025345A1 | 1998-06-11 | |||
| WO1999000734A1 | 1999-01-07 |
Other References:
JPN4000004569; 'ＳＬＤＲＡＭ，綿密なタイミング調整で高速・大容量化（下）' 日経エレクトロニクス Ｍ３ Ｎ７１２, 19980323, Ｐ１７５-１８３
Attorney, Agent or Firm:
Kosaku Sugimura