Title:
トランジスタ構成、トランジスタ構成をデータメモリとして動作するための方法、およびトランジスタ構成製造するための方法
Document Type and Number:
Japanese Patent JP2004533126
Kind Code:
A
Abstract:
The invention relates to a transistor arrangement having a substrate and a vertical transistor comprising: a first electrode region, a second electrode region arranged essentially above the latter, and, in between, a channel region, and also a gate region beside the channel region and, in between, an electrically insulating layer sequence, wherein two mutually spatially separate sections of the electrically insulating layer sequence in each case serve for the storage of charge carriers.
Inventors:
Hoffman, Franz
Villa, joseph
Villa, joseph
Application Number:
JP2003509546A
Publication Date:
October 28, 2004
Filing Date:
June 20, 2002
Export Citation:
Assignee:
Infineon Technolgies SC300 GmbH & Co.KG
International Classes:
G11C11/56; G11C16/04; H01L21/336; H01L21/8246; H01L21/8247; H01L27/115; H01L27/11553; H01L27/11568; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita
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