Title:
集積回路のチップ設計
Document Type and Number:
Japanese Patent JP2005502133
Kind Code:
A
Abstract:
Method of developing a model of a circuit design including the steps of generating four different path-tracing runs, creating four arcs from the four different path-tracing runs, and combining the four arcs into two separate models. Also, a method of adjusting timing of a clock signal provided to a first block and a second block where data signals travel via a first path from the first block to the second block and data signals travel via a second path from the second block to the first block and the time for the data signals to travel the first path is greater than the time for the data signals to travel the second path. The clock signal provided to the second block relative to the clock signal provided to the first block is delayed by an amount that is a function of the difference between the time for the data signals to travel the first path and the time for the data signals to travel the second path.
Inventors:
Williams Ted Yi
Fairlow Jonathan
Tovey Di Forest
Zang Lewis
Fairlow Jonathan
Tovey Di Forest
Zang Lewis
Application Number:
JP2003525521A
Publication Date:
January 20, 2005
Filing Date:
August 29, 2002
Export Citation:
Assignee:
Morfix Technology, Inc.
International Classes:
G06F17/50; H01L21/82; (IPC1-7): G06F17/50; H01L21/82
Attorney, Agent or Firm:
Sadao Kumakura
Fumiaki Otsuka
Toshio Imajo
Takaki Nishijima
Fumiaki Otsuka
Toshio Imajo
Takaki Nishijima