Title:
低減されたクロックジッタを備える位相ロックループ
Document Type and Number:
Japanese Patent JP2005516520
Kind Code:
A
Abstract:
The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.
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Inventors:
Nauta Blam
Funde Bake Remkoshi H
Vauchel Cicero S
Funde Bake Remkoshi H
Vauchel Cicero S
Application Number:
JP2003565053A
Publication Date:
June 02, 2005
Filing Date:
January 20, 2003
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
H03L7/18; H03L7/095; H03L7/107; H03L7/197; H03L7/089; (IPC1-7): H03L7/18
Attorney, Agent or Firm:
Susumu Tsugaru
Akihiko Miyazaki
Fueda Shusen
Akihiko Miyazaki
Fueda Shusen