Title:
積層ダイ半導体装置
Document Type and Number:
Japanese Patent JP2005519471
Kind Code:
A
Abstract:
A stacked multichip package ( 100 ) has a base carrier ( 102 ) having a top side ( 108 ) and a bottom side ( 110 ), a bottom integrated circuit die ( 104 ) having a bottom surface ( 112 ) attached to the base carrier top side ( 108 ), and an opposing, top surface ( 114 ). The top surface ( 114 ) has a peripheral area including a plurality of first bonding pads and a central area ( 120 ). A bead ( 124 ) is formed on the top surface ( 114 ) of the bottom die ( 104 ) between the peripheral area and the central area ( 120 ). A top integrated circuit die ( 106 ) having a bottom surface is positioned over the bottom die ( 104 ) and the bottom surface of the top die ( 106 ) is attached to the top surface ( 114 ) of the bottom die ( 104 ) via the bead ( 124 ). The bead ( 124 ) maintains a predetermined spacing between the bottom die ( 104 ) and the top die ( 106 ) so that wirebonds of first wires ( 122 ) connecting the bottom die ( 104 ) to the base carrier ( 102 ) are not damaged when the top die ( 106 ) is attached to the bottom die ( 104 ).
Inventors:
Low, you
Alipin, Azhar Bin
Chu, Kong Bee
Alipin, Azhar Bin
Chu, Kong Bee
Application Number:
JP2003573701A
Publication Date:
June 30, 2005
Filing Date:
February 07, 2003
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
H01L25/18; H01L25/065; H01L25/07; (IPC1-7): H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP2002057272A | 2002-02-22 | |||
| JPH05109786A | 1993-04-30 | |||
| JP2003179200A | 2003-06-27 | |||
| JP2001060657A | 2001-03-06 | |||
| JPH08288455A | 1996-11-01 | |||
| JPH08279591A | 1996-10-22 | |||
| JPH06350010A | 1994-12-22 |
Attorney, Agent or Firm:
Mamoru Kuwagaki