Title:
フレーム同期化デバイス及び方法
Document Type and Number:
Japanese Patent JP2006511142
Kind Code:
A
Abstract:
Disclosed is a frame synchronizing device and method for a binary data transmission system wherein digital data are transmitted as a serial bit stream organized into frames, each frame including a pre-defined frameheader, wherein said serial bit stream is inputted into a serial input portion of a serial input parallel output shift register means having at least as many stages as the number of bits of a frame, and said frames are outputted in a consecutive order from a parallel output portion of said shift register means. The particularity of the present invention is that it is detected whether or not a frameheader is present in the output of said parallel output portion, and, if not, the outputting of a frame from said parallel output portion is delayed by at least one time period which is needed for shifting a bit in said serial input portion from a stage to a next one, until synchronization is reached.
Inventors:
Marco, van, foot
Johannes P.A.Frambach
Johannes P.A.Frambach
Application Number:
JP2004561751A
Publication Date:
March 30, 2006
Filing Date:
November 18, 2003
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
H04J3/00; H04J3/06; H04L7/08
Domestic Patent References:
| JPH04170116A | 1992-06-17 | |||
| JPH04247735A | 1992-09-03 | |||
| JP2002176418A | 2002-06-21 | |||
| JPH01105629A | 1989-04-24 | |||
| JPH07202865A | 1995-08-04 | |||
| JPH07226730A | 1995-08-22 |
Foreign References:
| EP0397142A1 | 1990-11-14 |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki