Title:
最適なフィンガー間結合のための最小寸法のフルシリサイドMOSドライバ及びESD保護の設計
Document Type and Number:
Japanese Patent JP2006518941
Kind Code:
A
Abstract:
An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.
Inventors:
Margens, Melgens
Felhahege, Cohen Gerald Maria
Russ, Cornelius Christian
John Armor
Joswiack, Philip, Chesslaw
Keppens, Burt
Felhahege, Cohen Gerald Maria
Russ, Cornelius Christian
John Armor
Joswiack, Philip, Chesslaw
Keppens, Burt
Application Number:
JP2006503770A
Publication Date:
August 17, 2006
Filing Date:
February 19, 2004
Export Citation:
Assignee:
Sarnoff Corporation
Sarnoff Europe BV
Sarnoff Europe BV
International Classes:
H01L27/06; H01L21/822; H01L21/8234; H01L23/62; H01L27/02; H01L27/04; H01L29/06; H01L29/10; H01L29/417; H01L29/423; H01L29/49; H01L29/78; H02H
Attorney, Agent or Firm:
Yuichi Yamada
Masakazu Noda
Masakazu Noda