Title:
電源及び制御がセグメント化されたメモリシステム
Document Type and Number:
Japanese Patent JP2007517354
Kind Code:
A
Abstract:
A memory device having memory cells supplied with a separate higher voltage power than the separate power supplied to memory logic, and a lower power state that entails removing power from at least some of the logic such that refresh operations to preserve the contents of the memory cells continue to take place, but at least some of the interface to the memory device is powered down to reduce power consumption.
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Inventors:
Ellis, robert, em
Mooney, Stephen, Earl
Kennedy, Joseph, Tea
Mooney, Stephen, Earl
Kennedy, Joseph, Tea
Application Number:
JP2006547428A
Publication Date:
June 28, 2007
Filing Date:
December 22, 2004
Export Citation:
Assignee:
Intel Corporation
International Classes:
G11C11/401; G11C5/00; G11C5/14; G11C11/406; G11C11/4074
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Koichi Sugiyama
Shinsuke Onuki
Tadashige Ito
Koichi Sugiyama