Title:
PLLを使用する較正済み弛張発振器
Document Type and Number:
Japanese Patent JP2013528981
Kind Code:
A
Abstract:
A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.
Inventors:
Pancholi, Dipack
Obindra, Babin
Prasard, Naidu
Boggia, Surikanto
Sabineni, Sriniba salao
Naradasi, Jayapura Cush
Obindra, Babin
Prasard, Naidu
Boggia, Surikanto
Sabineni, Sriniba salao
Naradasi, Jayapura Cush
Application Number:
JP2013503792A
Publication Date:
July 11, 2013
Filing Date:
March 30, 2011
Export Citation:
Assignee:
SanDisk Technology Inc.
International Classes:
H03L7/093; G06F1/08; H03K3/0231; H03K4/06; H03L7/10
Domestic Patent References:
| JP2001211070A | 2001-08-03 | |||
| JP2002535908A | 2002-10-22 | |||
| JPH1127142A | 1999-01-29 | |||
| JP2001332969A | 2001-11-30 | |||
| JP2001211070A | 2001-08-03 | |||
| JP2002535908A | 2002-10-22 | |||
| JPH1127142A | 1999-01-29 | |||
| JP2001332969A | 2001-11-30 |
Foreign References:
| US20090316847A1 | 2009-12-24 | |||
| US6798299B1 | 2004-09-28 | |||
| US20090316847A1 | 2009-12-24 | |||
| US6798299B1 | 2004-09-28 |
Attorney, Agent or Firm:
Toshi Inoguchi