Title:
DECODER, RECEIVER AND ELECTRONIC APPARATUS
Document Type and Number:
Japanese Patent JP2018064276
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To reduce power consumption of decoder.SOLUTION: A decoder has a first circuit and a second circuit for holding data. The second circuit has a first transistor, a second transistor, and a third transistor. The first and second transistors have an oxide semiconductor in a channel formation region. The third transistor has silicon in the channel formation region. Gate of the second transistor is electrically connected with one of the source or drain of the first transistor, and the gate of the third transistor is electrically connected with one of the source or drain of the second transistor. The decoder has a function for switching supply and shutdown of power supply to the semiconductor device according to the packet ID of the header of the data, and performing data evacuation or restoration between the first and second circuits.SELECTED DRAWING: Figure 4
Inventors:
AOKI TAKESHI
KOZUMA MUNEHIRO
KUROKAWA YOSHIMOTO
KOZUMA MUNEHIRO
KUROKAWA YOSHIMOTO
Application Number:
JP2017196670A
Publication Date:
April 19, 2018
Filing Date:
October 10, 2017
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB CO LTD
International Classes:
H03K3/037; H04N21/438
Domestic Patent References:
| JP2014112827A | 2014-06-19 | |||
| JP2015062218A | 2015-04-02 | |||
| JP2017041877A | 2017-02-23 |