Title:
LEVEL SHIFT CIRCUIT
Document Type and Number:
Japanese Patent JP2019050550
Kind Code:
A
Abstract:
To provide a level shift circuit capable of improving a duty.SOLUTION: According to one embodiment, provided is a level shift circuit that has a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a third PMOS transistor, a second NMOS transistor, a fourth PMOS transistor, and a potential adjustment circuit. In the first PMOS transistor, a first node is electrically connected with its gate, and a second node is electrically connected with its source, and an output terminal in electrically connected its drain. In the first NMOS transistor, the first node is electrically connected with its gate, and the output terminal is electrically connected with its drain. In the second PMOS transistor, a third node is electrically connected with its gate, a second power supply potential is electrically connected with its source, and the second node is electrically connected with its drain. The potential adjustment circuit is at least electrically connected with the second node.SELECTED DRAWING: Figure 1
More Like This:
Inventors:
YAGI TOSHIHIRO
Application Number:
JP2018049762A
Publication Date:
March 28, 2019
Filing Date:
March 16, 2018
Export Citation:
Assignee:
TOSHIBA MEMORY CORP
International Classes:
H03K19/0175
Attorney, Agent or Firm:
Sakai International Patent Office