Title:
POWER INVERTER CIRCUIT
Document Type and Number:
Japanese Patent JP2019057993
Kind Code:
A
Abstract:
To prolong a time during which an upper FET is turned on, thereby reducing a loss, in a power inverter circuit.SOLUTION: In a power inverter circuit, a plurality of series circuits each comprising a lower FET and an upper FET are connected in parallel between high-potential input wiring 12 and low-potential wiring 16. A diode is connected in parallel to each upper FET. A first terminal of a main reactor 22 is connected to the high-potential input wiring, a first sub reactor 24 is connected between a second terminal of the main reactor and a drain of a first lower FET 31, and a second sub reactor 26 is connected between the second terminal of the main reactor and a drain of a second lower FET 33. A first state where the first lower FET is turned on, a second state where both lower FETs are turned off, a third state where the second lower FET is turned on, and a fourth state where both lower FETs are turned off repeatedly appear, in the order. A first upper FET 32 is maintained in an on state from the middle of a period of the second state to the middle of a period of the third state.SELECTED DRAWING: Figure 4
Inventors:
TOGYO KEN
Application Number:
JP2017180600A
Publication Date:
April 11, 2019
Filing Date:
September 20, 2017
Export Citation:
Assignee:
TOYOTA MOTOR CORP
International Classes:
H02M3/155; H02M7/48
Domestic Patent References:
| JP2007159177A | 2007-06-21 | |||
| JPH1169802A | 1999-03-09 | |||
| JP2017063604A | 2017-03-30 | |||
| JP2011167040A | 2011-08-25 |
Foreign References:
| US8513829B1 | 2013-08-20 | |||
| WO2017081971A1 | 2017-05-18 | |||
| WO2009081561A1 | 2009-07-02 |
Attorney, Agent or Firm:
Kaiyu International Patent Office