Title:
SEMICONDUCTOR DEVICE, SEMICONDUCTOR DESIGN DEVICE, AND SEMICONDUCTOR TEST DEVICE
Document Type and Number:
Japanese Patent JP2019168297
Kind Code:
A
Abstract:
To conduct a scan test at a low power consumption and a high speed without reducing the quality of the test.SOLUTION: A semiconductor device comprises: a circuit block that has a scan chain circuit for a scan test; and a clock gating circuit that switches whether to supply a clock signal to the scan chain circuit on the basis of an enable signal. The circuit block has a bypass route that bypasses the scan chain circuit, and a selection circuit that selects any one of an output signal from the scan chain circuit and a signal passing through the bypass route on the basis of the enable signal.SELECTED DRAWING: Figure 1
Inventors:
SUGIMOTO MASAHIKO
Application Number:
JP2018055266A
Publication Date:
October 03, 2019
Filing Date:
March 22, 2018
Export Citation:
Assignee:
TOSHIBA CORP
TOSHIBA ELECTRONIC DEVICES & STORAGE CORP
TOSHIBA ELECTRONIC DEVICES & STORAGE CORP
International Classes:
H01L21/822; G01R31/28; H01L27/04
Attorney, Agent or Firm:
Hiroyuki Nagai
Yukitaka Nakamura
Yasukazu Sato
Satoru Asakura
Takeshi Sekine
Akaoka Akira
Yasushi Kawasaki
Yukitaka Nakamura
Yasukazu Sato
Satoru Asakura
Takeshi Sekine
Akaoka Akira
Yasushi Kawasaki