Title:
SEMICONDUCTOR APPARATUS
Document Type and Number:
Japanese Patent JP2020120022
Kind Code:
A
Abstract:
To provide a technique for suppressing reduction in a Schottky barrier height of a pillar region and a surface electrode even if cracks occur at a triple point of contact between the surface electrode, an insulating resin film, and a metal film for solder joints.SOLUTION: An IGBT range 102 of a semiconductor substrate 10 is partitioned into a formation range 102a, in which a pillar region 16 is provided, and a non-formation range 102b, in which the pillar region 16 is not provided. The non-forming range 102b of the IGBT range 102 is disposed in a range including just below a triple point where an emitter electrode 24, an insulating resin film 26, and a metal film 28 for solder joints are in contact with each other.SELECTED DRAWING: Figure 2
Inventors:
HASHIMOTO NAOKI
SOENO AKITAKA
SOENO AKITAKA
Application Number:
JP2019011016A
Publication Date:
August 06, 2020
Filing Date:
January 25, 2019
Export Citation:
Assignee:
TOYOTA MOTOR CORP
International Classes:
H01L29/739; H01L21/336; H01L21/822; H01L21/8234; H01L27/04; H01L27/06; H01L27/088; H01L29/12; H01L29/78; H01L29/861; H01L29/868; H01L29/872
Attorney, Agent or Firm:
Kaiyu International Patent Office