Title:
ENCODING CIRCUIT, DECODING CIRCUIT, ENCODING METHOD, AND DECODING METHOD
Document Type and Number:
Japanese Patent JP2020188357
Kind Code:
A
Abstract:
To provide an encoding circuit, a decoding circuit, an encoding method, and a decoding method capable of reducing power consumption without reducing noise immunity.SOLUTION: An encoding circuit includes: an assigning unit configured to assign a symbol corresponding to a value of each of bit strings in a frame in a constellation, to the bit strings; a converter configured to convert a value of each of the bit strings other than a first bit string such that a larger assignment is allocated to a symbol closer to a center; a first inserting unit configured to generate an error correcting code for correcting an error of the bit strings and insert the generated error correcting code into the first bit string; a selecting unit configured to select a bit string of a generation source of the error correcting code; a switching unit configured to perform switching between a first time period in which the error correcting code is inserted into the first bit string and another second time period in a period of the frame; and a controller configured to control the switching unit and the selecting unit so that, in the first time period, the error correcting code is generated from each bit string other than the first bit string, and, in the second time period, the error correcting code is generated from the second bit string.SELECTED DRAWING: Figure 16
Inventors:
KOGANEI YOHEI
SUGITANI JUICHI
SUGITANI JUICHI
Application Number:
JP2019091371A
Publication Date:
November 19, 2020
Filing Date:
May 14, 2019
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H04L1/00; H04L27/00; H04L27/34
Attorney, Agent or Firm:
Shuhei Katayama