Title:
PLL CIRCUIT
Document Type and Number:
Japanese Patent JP2021002800
Kind Code:
A
Abstract:
To provide a PLL circuit capable of shortening a settling time as much as possible while maintaining good phase noise characteristics.SOLUTION: When the PLL circuit is locked from a predetermined low-frequency fL to a predetermined high-frequency fH, a charge pump energizes a charge current Icha to a control node of a VCO from the first timing t1a, which starts the lock from the low-frequency fL to the high-frequency fH. Thereafter, an offset current draw unit converges a phase comparison output of the phase comparator to become a steady phase difference by drawing an offset current Ioffa of a predetermined percentage of the charge current Icha from a control node Nin of the VCO at or after the second timing t2a at a predetermined time Taa after the first timing t1a.SELECTED DRAWING: Figure 3
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Inventors:
USUKINU TATSUNORI
Application Number:
JP2019116473A
Publication Date:
January 07, 2021
Filing Date:
June 24, 2019
Export Citation:
Assignee:
DENSO CORP
International Classes:
H03L7/107; H03L7/12
Domestic Patent References:
| JP2005198083A | 2005-07-21 | |||
| JP2005260866A | 2005-09-22 | |||
| JP2004207860A | 2004-07-22 | |||
| JP2008530955A | 2008-08-07 |
Foreign References:
| WO2019073841A1 | 2019-04-18 | |||
| US20180048322A1 | 2018-02-15 | |||
| WO2018116347A1 | 2018-06-28 | |||
| US20050280475A1 | 2005-12-22 |
Attorney, Agent or Firm:
Patent Business Corporation Sato International Patent Office