Title:
CLOCK GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP2021100232
Kind Code:
A
Abstract:
To provide a circuit that generates a clock having a frequency that changes such that a charging current becomes constant by solving a problem in which, when a large-capacity capacitor is charged using a charge pump circuit (SC power supply) driven by a constant frequency clock, a large inrush current is generated and an increasing rate of an output voltage (voltage of the capacitor to be charged) decrease with time, making the output voltage slowly approach a steady value, such that a charging time becomes longer.SOLUTION: A clock generating circuit according to the present invention includes two sawtooth wave generation circuits with different generation frequencies, and an output voltage V1 of a first high-speed sawtooth wave generation circuit is inverted such that amplitude of the output voltage V1 of the first high-speed sawtooth wave generation circuit becomes an absolute value of an output voltage V2 of a second low-speed sawtooth wave generation circuit, and thereby, a clock frequency f that increases in inverse proportion to (charging time tmax/charging coefficient α-time t) is generated.SELECTED DRAWING: Figure 2
Inventors:
OTA ICHIRO
TERADA SHINYA
TERADA SHINYA
Application Number:
JP2019240167A
Publication Date:
July 01, 2021
Filing Date:
December 19, 2019
Export Citation:
Assignee:
INST NATIONAL COLLEGES TECH JAPAN
International Classes:
H03K3/02; H03K3/0231; H03K4/56