Title:
MEMORY SYSTEM
Document Type and Number:
Japanese Patent JP2021149416
Kind Code:
A
Abstract:
To provide a memory system that improves the compressive performance of a dictionary type compression circuit.SOLUTION: A compression circuit 50 of a memory system has: a history buffer 100; a hash calculation circuit 110; a read pointer table 120; a history buffer writing circuit 130; a read pointer writing circuit 140; a read pointer reading circuit 150; a history buffer reading circuit 160; and match circuits (184, 170) that, as a result of comparison between an input data column and a match candidate data column, when the data columns at least partially match each other, replaces the input data column with reference information for referring to the match candidate data column. The memory system executes reading of a read pointer with the read pointer reading circuit and reading of an input data column with the history buffer reading circuit, after the completion of writing of the read pointer with the read pointer writing circuit and writing of the input data column with the history buffer writing circuit.SELECTED DRAWING: Figure 2
Inventors:
KODAMA SHO
NAKANISHI KEIRI
OIKAWA KOHEI
YASHIMA DAISUKE
SUMIYOSHI MASATO
FUKAZAWA YOHEI
NAKANISHI KEIRI
OIKAWA KOHEI
YASHIMA DAISUKE
SUMIYOSHI MASATO
FUKAZAWA YOHEI
Application Number:
JP2020047738A
Publication Date:
September 27, 2021
Filing Date:
March 18, 2020
Export Citation:
Assignee:
KIOXIA CORP
International Classes:
G06F12/04
Domestic Patent References:
| JP2016052046A | 2016-04-11 | |||
| JP2019029023A | 2019-02-21 |
Foreign References:
| US20170192709A1 | 2017-07-06 | |||
| US20140266816A1 | 2014-09-18 |
Attorney, Agent or Firm:
Takahashi Hayashi & Partners