Title:
【発明の名称】薄膜トランジスタ
Document Type and Number:
Japanese Patent JP2507031
Kind Code:
B2
Abstract:
A thin film transistor including a substrate (10) upon which are supported a gate electrode layer (12), a gate dielectric layer (14), at least one finger-like source electrode (18), a semiconductor layer (16, 24) overlying the gate dielectric layer and at least partially surrounding the source electrode, and a drain electrode layer (26) contiguous with the semiconductor layer. The length of the current path between the source electrode and the drain electrode layer is defined by a first path portion located at the semiconductor/gate dielectric interface and extending, between adjacent source elements, substantially parallel to the interface, and a second path portion whose length is substantially coextensive with the thickness of the semiconductor layer.
Inventors:
MAIKERU HATSUKU
JON GEARII SHOO
MAIKERU SHAA
JON GEARII SHOO
MAIKERU SHAA
Application Number:
JP6910889A
Publication Date:
June 12, 1996
Filing Date:
March 20, 1989
Export Citation:
Assignee:
XEROX CORP
International Classes:
H01L29/78; H01L29/786; (IPC1-7): H01L29/786
Attorney, Agent or Firm:
Minoru Nakamura (7 outside)