Title:
【発明の名称】半導体装置の製造方法
Document Type and Number:
Japanese Patent JP2516428
Kind Code:
B2
Abstract:
PURPOSE:To facilitate ion implantation by etching a second layer gate electrode material formed on a semiconductor substrate surface, an insulating layer surface, and the upper surface of first layer gate electrodes as far as the upper surface of the first layer gate electrodes, eliminating the insulating layer, and forming a second layer gate electrodes between the first layer gate electrodes. CONSTITUTION:After an insulating layer 6 is formed on the surface of a semiconductor substrate and the surface of a first layer gate electrodes 5 formed on the said substrate surface, the insulating layer 6 is anisotropically etched, and left only on the side surfaces of the first layer gate electrodes 5; a second layer gate electrode material 8 is deposited on the surface of the left insulating, layer 6, the upper surface of the first layer gate electrodes 5, and the surface of the semiconductor substrate 1; said material 8 is etched almost as far as the upper surface of the first layer gate electrodes 5; then the left insulating layer 6 is eliminated, thereby forming a second layer gate electrode 8a between the first layer gate electrodes 5. As a result, the first layer gate electrodes 5 and the second layer gate electrodes 8a do not overlap, so that unevenness is not present on the upper surface of the semiconductor substrate 1 and a flat structure is obtained. Thereby ion implantation is facilitated.
Inventors:
FUJIMOTO KOJI
OOSHIMA MASATOSHI
OOSHIMA MASATOSHI
Application Number:
JP11705989A
Publication Date:
July 24, 1996
Filing Date:
May 10, 1989
Export Citation:
Assignee:
SHARP KK
International Classes:
H01L21/768; H01L21/336; H01L21/8246; H01L27/112; H01L29/417; H01L29/78; (IPC1-7): H01L21/8246; H01L27/112
Domestic Patent References:
| JP51151089A |
Attorney, Agent or Firm:
Koji Onishi