Title:
【発明の名称】半導体集積回路
Document Type and Number:
Japanese Patent JP2557411
Kind Code:
B2
Abstract:
A semiconductor integrated circuit including delay means for generating an output signal delayed by a predetermined time with respect to an input signal when a logic level of said input signal changes in a first direction. The delay means receives a control signal and generates an internal control signal which is delayed by a predetermined time with respect to the control signal when a logic level of the control signal changes in a first direction, including a capacitor for delaying the control signal and a resistor having one end and having the other end connected to the capacitor.
Inventors:
NAKAI HIROTO
IWAHASHI HIROSHI
ASANO MASAMICHI
KUMAGAI SHIGERU
IWAHASHI HIROSHI
ASANO MASAMICHI
KUMAGAI SHIGERU
Application Number:
JP24676387A
Publication Date:
November 27, 1996
Filing Date:
September 30, 1987
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/8238; G11C11/407; G11C11/4076; H01L27/092; H01L27/10; H03H11/26; H03K5/1252; H03K5/13; H03K5/131; H03K5/133; H03K5/134; H03K5/135; H03K5/00; (IPC1-7): H01L21/8238; G11C11/407; H01L27/092; H01L27/10; H03K5/13
Domestic Patent References:
| JP5245247A | ||||
| JP4860447U | ||||
| JP60111126U | ||||
| JP5651662B2 |
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)