Title:
【発明の名称】信号ゲ-ト
Document Type and Number:
Japanese Patent JP2578330
Kind Code:
B2
Abstract:
One-bit stream of clocked control information is applied to the input(s) of delay means (L-1 to L-12), having a succession of signal takeoff points with the delay between successive takeoff points being the same (e.g., twice a period ( ), at the clocking frequency, fCL). Each takeoff point is linked to a respectively different input of an "and" gate (30). The "and" gate output is coupled to one input of a succession of two-input "or" gates (0-2 to 0-16), with the other input of each of said "or" gates coupled to the output of an associated one of a plurality of delay devices, (D-1 to D-15), each of the latter imparting the same delay ( ) (e.g., corresponding to a period of fCL). The output of each of the remainder of the succession is coupled to the other input of the next succeeding "or" gate in the succession. The input of the delay device (D-1) associated with the first "or" gate (0-2) of the succession is coupled to receive the output of an additional "or" gate is responsive to the output of the "and" . gate (30), while the other input thereof is not signal- responsive, being maintained at "0" level.
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Inventors:
REOHORUDO ARUBAATO HAAUTSUDO
KAAKU ANTONII ROO
KAAKU ANTONII ROO
Application Number:
JP8726686A
Publication Date:
February 05, 1997
Filing Date:
April 17, 1986
Export Citation:
Assignee:
AARU SHII EE TOMUSON RAISENSHINGU CORP
International Classes:
H03K5/05; H03K5/153; H03K5/19; H03K5/26; H04N9/78; (IPC1-7): H03K5/153; H03K5/19; H04N9/78
Domestic Patent References:
| JP61251318A | ||||
| JP61251394A | ||||
| JP61177877A |
Attorney, Agent or Firm:
Katsunori Watanabe