Title:
【発明の名称】アドレス変換機構
Document Type and Number:
Japanese Patent JP2586160
Kind Code:
B2
Abstract:
PURPOSE:To speed up address conversion by providing a means judging whether an address is a virtual one or not and a means generating the address indexing the entry of first TLB (translation look-aside buffer). CONSTITUTION:If it is judged that the virtual address which is conversion- requested is the virtual address related on the operand of plural operands use instruction when the virtual address is conversion-requested, the address indexing the entries 1-3 of first TLB 5, which are previously allocated in correspondence with the operand number of the operand is generated. Consequently, respectively different areas of first TLB 5 are used as for the address conversion of respective operands of the plural operands use instruction, and congestion as against the same entry of first TLB is avoided in respective operands. Thus, the hit rate of first TLB is improved and address conversion at the execution time of the plural operands use instruction is attained at high speed.
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Inventors:
KOTO MASATOSHI
Application Number:
JP1418290A
Publication Date:
February 26, 1997
Filing Date:
January 24, 1990
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F12/10; (IPC1-7): G06F12/10
Domestic Patent References:
| JP1226056A | ||||
| JP5996587A | ||||
| JP63168752A | ||||
| JP5661083A | ||||
| JP5782269A |
Attorney, Agent or Firm:
Sakai Hiromi