Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JP2599493
Kind Code:
B2
Abstract:
PURPOSE:To reduce the on resistance with the same number of processes and the same high breakdown resistance by providing a second conductivity type of extended drain region between a second type of source region and a drain contact region, and providing a plurality of conductivity type regions, which pass through the surface and reach the interior of semiconductor substrate, apart in this extended drain region. CONSTITUTION:Plural pieces of PT regions 3 are provided apart, and the depth of each PT region reaches the interior of a substrate 4 through an extended drain region 2. Therefore, the high-concentration area at the surface of the silicon substrate 4 of extended drain region 2 where a current flows also becomes the region where a current flows, so on resistance reduces. Hereupon, not to cause the reduction of breakdown strength, the intervals between plural pieces of PT regions 3 are such ones that the depletion layers are shut in the extended drain region at gate off, and the respective PT regions 3 are connected to the silicon substrate electrically. Hereby, on resistance reduces to about 70% as compared with a conventional one.
Inventors:
Kawasaki Hideo
Yuji Yamanishi
Hiroshi Yata
Yamaguchi Makoto
Hiroyuki Shindo
Toshihiko Uno
Yuji Yamanishi
Hiroshi Yata
Yamaguchi Makoto
Hiroyuki Shindo
Toshihiko Uno
Application Number:
JP22578490A
Publication Date:
April 09, 1997
Filing Date:
August 27, 1990
Export Citation:
Assignee:
Matsushita Electronics Industrial Co., Ltd.
International Classes:
H01L29/06; H01L29/78; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Tomoyuki Takimoto