Title:
【発明の名称】半導体集積回路の製造方法
Document Type and Number:
Japanese Patent JP2600493
Kind Code:
B2
Abstract:
PURPOSE:To enable a groove of a large aspect ratio which can not be filled with SiO2 to be filled, to cope with the micronization of a PROM, and to prevent a parasitic MOS transistor from occurring by a method wherein a groove is buried with a BPSG film. CONSTITUTION:A polycrystalline silicon film 16, a second gate insulating film 15, a polycrystalline silicon 14, a first gate insulating film 13, and a P-type silicon substrate 1 where a groove is provided in a PROM cell forming region are removed through an anisotropic etching method by the use of a lithography technique, whereby PROM cell transistor isolating grooves 18A and 18B 0.6mum in width and 1.2-1.5mum in depth are formed. A silicon thermal oxide film 17 is formed inside the grooves 18A and 18B and on the surface of the polysilicon film 16 as thick as 200Angstrom or so through a thermal oxidation process carried out at a temperature of 900 deg.C. Then, a BPSG film 19 which contains 8mol% of boron and 4mol% of phosphorus is made to grow through a CVD method, which is thermally treated at a high temperature of 900 deg.C for 30 minutes to be filled into the grooves 18A and 18B and to flatten the surface of the board 1.
Inventors:
Takeshi Okazawa
Application Number:
JP40891890A
Publication Date:
April 16, 1997
Filing Date:
December 28, 1990
Export Citation:
Assignee:
NEC
International Classes:
H01L21/8247; H01L21/76; H01L27/10; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L21/76; H01L29/788; H01L29/792
Domestic Patent References:
| JP6243180A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)