Title:
【発明の名称】多段集積デコーダ装置
Document Type and Number:
Japanese Patent JP2603205
Kind Code:
B2
Abstract:
The invention permits as a special function the simultaneous activation of some or all of its outputs. Where used as a bit line decoder, consequently some or all bit lines (including any redundant bit lines there may be) of a block of memory cells of a semiconductor memory can be activated.
Inventors:
Kurt, Hoffman
Liner, Claus
Oskar, Kowaliq
Manfred, Paul
Liner, Claus
Oskar, Kowaliq
Manfred, Paul
Application Number:
JP5919688A
Publication Date:
April 23, 1997
Filing Date:
March 11, 1988
Export Citation:
Assignee:
Siemens, Actien Gezershaft
International Classes:
G11C11/413; G11C8/00; G11C8/12; G11C11/401; G11C11/407; G11C29/00; G11C29/34; H03M7/00; (IPC1-7): G11C29/00; G11C11/408; G11C11/413; H03M7/00
Domestic Patent References:
| JP61292298A |
Attorney, Agent or Firm:
Tomimura Kiyoshi