Title:
【発明の名称】キャッシュメモリ
Document Type and Number:
Japanese Patent JP2615113
Kind Code:
B2
Abstract:
PURPOSE:To realize high integration by storing the information of a cache memory with the use of a dynamic-type memory cell consisting of an address selecting MOSFET and a information storing capacitor. CONSTITUTION:In the dynamic-type memory cell consisting of an address selecting MOSFETQm and an information storing capacitor CS, an address signal in a memory is stored into the memory cell linked to word lines W0-Wj. Unit sense amplifiers USA provided at a pair of complementary bit lines B0 and inverted B0-Bi and inverted Bi amplify the memory information from the memory cell, and refreshes (restores) it. A precharging circuit consists of an MOSFETQ3 to short-circuit the lines, for example, B0 and inverted B0, and MOSFETQ4 and Q5 to transmit VCC/2 to the respective bit lines B0 and inverted B0. Precharging signals PC are supplied to Q-Q5. Selective signals Y0-Yi are supplied to MOSFETQ6 and Q7 and writing is carried out in synchronization with this.
Inventors:
Takahashi Yasushi
Application Number:
JP1065288A
Publication Date:
May 28, 1997
Filing Date:
January 22, 1988
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F12/08; G11C11/34; G11C11/401; (IPC1-7): G11C11/401; G06F12/08
Domestic Patent References:
| JP59116850A | ||||
| JP6267793A |
Other References:
インタフェース、Ｎｏ．１２３（１９８７−８）Ｐ．２４１−２５７
Attorney, Agent or Firm:
Shizuyo Tamamura (1 person outside)