Title:
多重端局装置の回線試験回路
Document Type and Number:
Japanese Patent JP2659427
Kind Code:
B2
Abstract:
PURPOSE:To prevent the occurrence of a malfunction in a test by providing the subject line testing circuit with a decision circuit, and even when a reset signal from a command register can not be properly received from an external circuit, writing a new command while clearing already written commands. CONSTITUTION:Whether a test command signal indicates a signal line test or a speech path test is decided with the decision circuit 71, and in the case of the signal line test, the test information is written in a signal line register 71 and the contents of a speech path register 72 are reset with a reset circuit 74. In the case of the speech path test, the reverse operation is executed. Thereby, test information precedently written in the registers 72, 73 are not left. Consequently, the generation of malfunction in the test due to the reading of the past test information can be prevented.
Inventors:
UCHIDA KATSUTO
HARADA KENJI
HARADA KENJI
Application Number:
JP3876489A
Publication Date:
September 30, 1997
Filing Date:
February 17, 1989
Export Citation:
Assignee:
FUJITSU KK
International Classes:
H04J3/14; H04L69/40; H04M3/26; (IPC1-7): H04J3/14; H04L12/24; H04L12/26; H04L29/14; H04M3/26
Attorney, Agent or Firm:
小林 隆夫