Title:
スキャン可能なフリップフロップ回路及びスキャンクロックの設定方法
Document Type and Number:
Japanese Patent JP2659952
Kind Code:
B2
Abstract:
PURPOSE:To prevent the operating speed from being deteriorated due to a wiring of a scan path, by executing a signal transfer by repeating state holding by a latch and dynamic state holding by a load capacity, by a two-phase clock, in a scan mode. CONSTITUTION:Transfer gates T1-T4 are controlled by a one-phase clock C in a system mode, and transfer gates T5-T7 are controlled by one of two- phase clocks A, B in a scan mode. In the case of the scan mode, when the clock C is in an OFF state, the clock B is in an ON state, and the clock A is in an OFF state, a scan data input SL is inputted to a latch, and when both the blocks B, A are OFF, the latch becomes a stable state. Subsequently, when the clock A becomes ON and the clock B becomes an OFF state, the load capacity of a scan data output SO is charged, by which the charge is held until both the clocks A, B become an OFF state in the next time, and a dynamic operation is executed.
Inventors:
HIRABAYASHI KANJI
Application Number:
JP8697587A
Publication Date:
September 30, 1997
Filing Date:
April 10, 1987
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
G01R31/28; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
外川 英明 （外１名）