Title:
【発明の名称】半導体メモリセル
Document Type and Number:
Japanese Patent JP2660111
Kind Code:
B2
Abstract:
A semiconductor memory cell comprises a cascade gate including a plurality of cascade-connected MOS transistors (Q1 to Q4) and having one end connected to a first node (N1), and a plurality of capacitors (C1 to C4) for data storage connected at one end to the MOS transistors (Q1 to Q4), respectively, at the end remote from the node (N1), and there is a predetermined regulation in relation of the capacitance of the capacitors.
Inventors:
TAKASE SATORU
KUSHAMA NATSUKI
FURUYAMA TOORU
KUSHAMA NATSUKI
FURUYAMA TOORU
Application Number:
JP4132191A
Publication Date:
October 08, 1997
Filing Date:
February 13, 1991
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
G11C11/405; G11C11/56; H01L21/8242; H01L27/108; (IPC1-7): G11C11/405; H01L21/8242; H01L27/108
Domestic Patent References:
| JP61162897A | ||||
| JP336762A | ||||
| JP358377A | ||||
| JP369092A | ||||
| JP43463A | ||||
| JP4351789A |
Other References:
ＮＩＫＫＥＩ ＭＩＣＲＯＤＥＶＩＣＥＳ（１９９１−３）Ｐ．８７−８８
Attorney, Agent or Firm:
Takehiko Suzue