Title:
【発明の名称】半導体回路
Document Type and Number:
Japanese Patent JP2690060
Kind Code:
B2
Abstract:
PURPOSE:To facilitate a circuit connection and to sufficiently enhance the substantial performance of each circuit by constituting each series connection point of 2 sets of series connection circuits to be output terminals for signal pairs subjected to level shift. CONSTITUTION:An intermediate level shift circuit (a) decreasing an input signal pair S, the inverse of S of an intermediate level into a signal pair SN, the inverse of SN of a lower desired intermediate level is by employing 2 sets of series circuits each comprising 2 N-channel MOS transistor(TR) TN, and an intermediate level shift circuit (b) increasing the input signal pair S, the inverse of S of the intermediate level into a signal pair SP, the inverse of SP of a higher desired intermediate level is constituted by employing 2 sets of series circuits each composed 2 P-channel MOS transistor(TR) TP. Then the gates of the TRs TN, TP receive the input signals S, the inverse of S and series connecting points of each set are used as output terminals. Thus, the connection of respective circuits is facilitated and the substantial performance of each circuit is sufficiently enhanced.
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Inventors:
Kazuto
Application Number:
JP22248889A
Publication Date:
December 10, 1997
Filing Date:
August 29, 1989
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K5/003; G11C11/407; G11C11/409; H03K5/00; H03K19/00; H03K19/0185; H03K19/0944; (IPC1-7): H03K19/0185; H03K5/003; H03K19/00; H03K19/0944
Domestic Patent References:
| JP5877318A | ||||
| JP5877319A |
Attorney, Agent or Firm:
Fumihiro Hasegawa