Title:
【発明の名称】半導体記憶装置及び半導体記憶装置からのデータ読み出し方法
Document Type and Number:
Japanese Patent JP2697665
Kind Code:
B2
Abstract:
For a nonvolatile multi-stage semiconductor memory device, a data reading sequence is given first, second, and third phases. During the first phase, a word line is driven to 2.25 V with a differential amplifier and a bias circuit activated to sense on or off of a selected memory cell. During the second phase, the word line is driven to 3.0 V with a differential amplifier and a bias circuit activated to sense on or off of the selected memory cell. This enables correct read out with a low operating voltage, such as 3.0 V, of data stored in semiconductor memory cells with a selected one of four threshold levels given to each datum. During the third phase, it is possible to use the differential amplifier and the bias circuit which are used during the first phase. Use of one differential amplifier alone is possible with two bias circuits used. Use of only first and second phases is also possible.
Inventors:
Kiyoshi Kazuhashi
Application Number:
JP7576695A
Publication Date:
January 14, 1998
Filing Date:
March 31, 1995
Export Citation:
Assignee:
NEC
International Classes:
G11C17/00; G11C7/06; G11C11/56; G11C16/02; (IPC1-7): G11C16/02
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)