Title:
【発明の名称】CMOSラッチ回路
Document Type and Number:
Japanese Patent JP2733578
Kind Code:
B2
Abstract:
A CMOS latch circuit is provided which eliminates the lowering of a high voltage level from a precharge/discharge data bus line caused by charge-sharing effect. The CMOS latch circuit is formed of a P-channel precharge transistor (P1), a P-channel drive transistor (P2), an N-channel drive transistor (N1), an N-channel enable transistor (N2), and a transmission gate (TG) for loading a complementary data input signal to a storage node (A) in response to true and complementary load signals. The latch circuit further includes output transistor devices formed of a pair of P-channel output transistors (P3, P4) and a pair of N-channel output transistors (N3, N4) which are all connected in series, and are responsive to true and complementary load signals and to true and complementary data output signals for maintaining the latch circuit in one of two states.
Inventors:
DONARUDO MONRO UORUTAAZU JUNIA
Application Number:
JP20931888A
Publication Date:
March 30, 1998
Filing Date:
August 22, 1988
Export Citation:
Assignee:
ADOBANSUTO MAIKURO DEIBAISHIZU INC
International Classes:
H03K3/356; (IPC1-7): H03K3/356
Attorney, Agent or Firm:
Fukami Hisaro (2 outside)