Title:
【発明の名称】マルチコンピュータのデータ伝送装置
Document Type and Number:
Japanese Patent JP2735599
Kind Code:
B2
Abstract:
PURPOSE:To simplify a system program by providing the above equipment with a means for inverting and outputting one prescribed bit in addresses outputted from the 1st and 2nd processors, in the 2nd period, and at the time of writing/reading out data in/from both the processors, outputting the address of the same prescribed storage area independently of the 1st and 2nd periods. CONSTITUTION:Only at the time of inputting a ready signal from a DP-RAM 3, a microcomputer 1 and a DSP 2 in the data transmitting equipment execute data writing/reading operation. The uppermost bit A10 of an address outputted from the computer 1 and the DSP 2 in the transfer equipment during the prescribed output period is inverted by an address switching control circuit 10. A clock with a prescribed frequency is inputted from a clock signal generating circuit 11 in the transfer equipment to a timing signal generating circuit 12, 'L' level and 'H' level phase signals PSs in the 1st and 2nd periods in data transfer processing are inputted to the circuit 10, the address is processed by the circuit 10, and the address of the same prescribed storage area is outputted.
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Inventors:
SUESHIGE KEIICHIRO
SEO NOBUHIDE
HARADA YASUHIRO
SEO NOBUHIDE
HARADA YASUHIRO
Application Number:
JP2019089A
Publication Date:
April 02, 1998
Filing Date:
January 30, 1989
Export Citation:
Assignee:
MATSUDA KK
International Classes:
G06F15/167; G06F12/02; G06F15/16; (IPC1-7): G06F15/167; G06F12/02
Domestic Patent References:
| JP1116861A |
Attorney, Agent or Firm:
Aoyama Ryo (1 person outside)