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Title:
【発明の名称】半導体装置の製造方法
Document Type and Number:
Japanese Patent JP2735601
Kind Code:
B2
Abstract:
PURPOSE:To provide a buried grid layer to a semiconductor layer only at an optional depth by a method wherein ions are implanted with a comparatively low ion energy usually used. CONSTITUTION:A mask pattern 12 is provided to a p-type Si substrate 11, and P ions are implanted in the direction of a crystal axis with an energy of 200keV so as to induce channeling. When ions are implanted taking advantage of channeling, an implantation range Rp increases ten times or so as long as that of a usual slant implantation, and an n-layer 13 (impurity distribution I) is obtained. In succession, B ions are similarly implanted in the direction of a crystal axis with an ion energy of 200keV or lower to make a implantation Rp shallow for the formation of a p<+>-layer (impurity distribution II). Then, when the p-type Si substrate 11 is thermally treated in an atmosphere of N2 to activate keeping the distribution of impurity concentration near Rp of a curve I unchanged, the overlapped parts of the concentration curves I and II offset each other and an n-type region (dotted line) small in width is formed in a depthwise direction of n-type, and a buried n-type grid layer serving as a countermeasure to an alpha-ray soft error is formed at a comparatively deep position.

Inventors:
TANAKA AKIRA
Application Number:
JP2862489A
Publication Date:
April 02, 1998
Filing Date:
February 09, 1989
Export Citation:
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Assignee:
OKI DENKI KOGYO KK
International Classes:
H01L21/265; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; H01L21/265; H01L21/8242
Domestic Patent References:
JP62131579A
Attorney, Agent or Firm:
Toshiaki Suzuki