Title:
【発明の名称】半導体集積回路
Document Type and Number:
Japanese Patent JP2757583
Kind Code:
B2
Abstract:
A semiconductor integrated circuit device is fabricated on a lightly doped n-type silicon substrate (11), and p-type wells (13/ 14) are formed in the silicon substrate, wherein a heavily doped n-type channel stopper (21) is formed in a surface portion (20) between the p-type wells for restricting a parasitic channel between the p-type wells, and the surface portion is doped at a predetermined impurity concentration larger than a remaining portion of the silicon substrate and smaller than the channel stopper so that a p-n junction hardly takes place between the inverted surface portion and the channel stopper.
Inventors:
NAKASHIBA YASUTAKA
Application Number:
JP13054791A
Publication Date:
May 25, 1998
Filing Date:
May 02, 1991
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H01L21/339; H01L21/76; H01L27/08; H01L27/148; H01L29/06; H01L29/762; H01L27/02; (IPC1-7): H01L27/148; H01L21/76; H01L27/08
Domestic Patent References:
| JP2220451A | ||||
| JP2226743A |
Attorney, Agent or Firm:
Yusuke Omi