Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JP2771880
Kind Code:
B2
Abstract:
PURPOSE:To improve accuracy and to accelerate speed in an LSI with high integration and low voltage by impressing a bias voltage to the gate of a transis tor for dividing potential in the first push-pull circuit to form the current ampli fier circuit of a reference current amplifier circuit and connecting the output end of the current amplifier circuit to the bias circuit of the second push-pull circuit. CONSTITUTION:Voltage difference between an input and an output is converted to a current through the transistor of a first complementary push-pull circuit 1 and by an amplified current in proportion to the converted current, a second complementary push-pull circuit 3 is driven. Therefore, while there is the voltage difference between the input and the output, the driving ability of the push-pull circuit 3 is improved and charging/discharging is exerted upon load capacity at high speed. Then, even in that case, the driving ability can be made the same for charging and discharging. Thus, a voltage supply circuit can be formed to be stably operated at high speed even by low voltage.
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Inventors:
NAKAGOME YOSHINOBU
ITO KYOO
ITO KYOO
Application Number:
JP4107690A
Publication Date:
July 02, 1998
Filing Date:
February 23, 1990
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
International Classes:
G11C11/407; G05F3/24; G11C11/401; G11C11/404; G11C11/413; H01L21/822; H01L27/04; H01L27/10; (IPC1-7): G11C11/407; G05F3/24; G11C11/401; G11C11/404; G11C11/413; H01L21/822; H01L27/04; H01L27/10
Domestic Patent References:
| JP3273594A | ||||
| JP63237287A | ||||
| JP63152087A | ||||
| JP6284490A |
Attorney, Agent or Firm:
Junnosuke Nakamura