Title:
【発明の名称】半導体メモリ装置のカラム冗長方法及びその回路
Document Type and Number:
Japanese Patent JP2777091
Kind Code:
B2
Abstract:
A column redundancy circuit and method of a semiconductor memory device. The column redundancy circuit comprises a programming element for programming a repair column address; a comparing element for comparing the programmed repair column address with a column address inputted from outside to thereby generate a redundancy enable control signal according to result of the comparison; a decoding element for decoding the repair column address signal to thereby generate a decoding signal; and a redundancy column select element for compounding the decoding signal and a data input signal to thereby enable a redundancy column select signal.
Inventors:
BOKU TETSUJU
Application Number:
JP21605495A
Publication Date:
July 16, 1998
Filing Date:
August 24, 1995
Export Citation:
Assignee:
SANSEI DENSHI KK
International Classes:
G11C29/00; G11C29/04; (IPC1-7): G11C29/00
Domestic Patent References:
| JP61294689A | ||||
| JP3276497A | ||||
| JP6203594A |
Attorney, Agent or Firm:
Takeshi Takatsuki