Title:
【発明の名称】速度変換回路
Document Type and Number:
Japanese Patent JP2791923
Kind Code:
B2
Abstract:
PURPOSE:To reduce the capacity of a memory tentatively storing a data signal to be subjected to speed conversion and to improve the characteristic of a circuit comparing the phase of a write clock of the memory with the phase of a read clock in the speed converter circuit multiplexing plural insert bits to each frame consecutively. CONSTITUTION:A signal from a read clock generating circuit 5 is inhibited for almost an equal interval by N-bits per frame with a read stop control signal 202 from a multiplex control circuit 7 resulting in a missing read clock 204 and it is used to read a transmission signal stored tentatively in a storage circuit 1. A read data string 203 is converted by a string conversion circuit 301, resulting in a data string 103 onto which a consecutive N-bit insert pulse is multiplexed, the insert bit is multiplexed by a multiplex circuit 6, from which a multiplexed signal 104 is obtained.
Inventors:
KURODA MASAYOSHI
FUKUDA SEIJI
FUKUDA SEIJI
Application Number:
JP11817191A
Publication Date:
August 27, 1998
Filing Date:
May 23, 1991
Export Citation:
Assignee:
NIPPON DENKI ENJINIARINGU KK
International Classes:
H04J3/00; H04J3/04; H04J3/07; H04L7/00; H04L29/08; (IPC1-7): H04J3/04; H04J3/00; H04J3/07; H04L7/00; H04L29/08
Domestic Patent References:
| JP457546A | ||||
| JP2237332A | ||||
| JP37437A | ||||
| JP5897938A | ||||
| JP1188127A | ||||
| JP3173233A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)