Title:
【発明の名称】表示コントローラ
Document Type and Number:
Japanese Patent JP2797435
Kind Code:
B2
Abstract:
A video display controller supplies a raster address signal to a video memory for sequentially reading out a series of video data codes, and comprises a first data register for memorizing a control data code indicative of a bit length to be circulated in a rewritable manner, a second register for memorizing a repetition rate code indicative of a repetition pattern of the raster address in a rewritable manner, a combination of a shift register and a selector supplied with the repetition rate code in synchronism with a frame clock signal and circulating the data bits of the repetition code indicated by the control data code in synchronism with a line clock signal and a raster counter responsive to an enable signal fed from the selector and latching the line clock signal for incrementing the raster address, wherein the raster address is incremented or maintained depending upon the data bit at a predetermined bit position serving as the enable signal, so that the series of video data codes are repeatedly read out from the video memory for enlarging visual images on a screen.
Inventors:
Shuhei Ito
Application Number:
JP13372289A
Publication Date:
September 17, 1998
Filing Date:
May 26, 1989
Export Citation:
Assignee:
Yamaha Corporation
International Classes:
G06F3/14; G09G5/00; G09G5/12; G09G5/18; G06F3/153; G09G5/391; H04N7/01; (IPC1-7): G09G5/18; G06F3/153; H04N7/01
Attorney, Agent or Firm:
Masatake Shiga (2 outside)