Title:
【発明の名称】マルチチャンネルデータ通信制御器
Document Type and Number:
Japanese Patent JP2812959
Kind Code:
B2
Abstract:
This invention provides a flexible, general-purpose, engine-based architecture for a multi-channel data communications controller. It can be customized to handle a wide range of protocols and other host system requirements with minimal reliance on the host's processing power. The always present time-critical tasks of transmitting and receiving serial data, as well as transmitting and receiving characters to/from the host, are handled quickly and efficiently by utilizing dedicated interface processors. This leaves the general purpose main engine less burdened with these time cricital tasks, enabling it to perform the relatively more complex (though less time critical) tasks of assembling and disassembling characters, as well as maintaining RAM-based data FIFOs and performing error-checking and other protocol-related tasks. Custon protocols can be implemented merely by re-microcoding the machine, without requiring modifications to the basic architecture of the chip, substantially reducing design time. The flexibility of this general purpose architecture enables controllers to be more customized to a particular user's requirements, resulting not only in faster performance by the controller itself, but also in far less reliance on the host's processing power. What could previously only be done by the host in software can now be done by the controller itself much more quickly.
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Inventors:
John Wishniskey
Cecil Kaprinski
Anthony o'tool
Shahin Hedayat
Shrikant Acaya
Cecil Kaprinski
Anthony o'tool
Shahin Hedayat
Shrikant Acaya
Application Number:
JP19472588A
Publication Date:
October 22, 1998
Filing Date:
August 05, 1988
Export Citation:
Assignee:
Cirrus Logic, Incorporated
International Classes:
H04L29/02; G06F13/38; H04L13/08; (IPC1-7): H04L29/02; H04L13/08
Domestic Patent References:
| JP61288246A |
Attorney, Agent or Firm:
Kazuo Kobashi (1 person outside)