【発明の名称】デジタルPLL装置

Title:

【発明の名称】デジタルPLL装置

Document Type and Number:

Japanese Patent JP2850949

Kind Code:

B2

Abstract:

A digital PLL apparatus includes a synchronization integrating circuit, an angle calculating circuit, and a digital PLL circuit. The synchronization integrating circuit determines a symbol timing by obtaining the maximum amplitude point of a correlation level during reception of a preamble. The angle calculating circuit outputs a phase theta c by performing an angle calculation every symbol timing determined by the synchronization integrating circuit. The digital PLL circuit receives the phase theta c from the angle calculating circuit and operates a phase locked loop, thereby obtaining an output phase.

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WO/2008/016224	PHASE DETECTION APPARATUS AND METHOD, PHASE LOCKED LOOP CIRCUIT AND CONTROL METHOD THEREOF, AND SIGNAL REPRODUCING APPARATUS AND METHOD

Inventors:

FUKUSHI MIKIO

Application Number:

JP32765195A

Publication Date:

January 27, 1999

Filing Date:

December 15, 1995

Export Citation:

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Assignee:

NIPPON DENKI KK

International Classes:

H03L7/08; H04B1/707; H04B1/7073; H04L7/033; H04L7/04; H04L7/10; H04L27/227; (IPC1-7): H04L7/10; H03L7/08; H04L7/033; H04L27/227

Domestic Patent References:

JP6120997A
JP7202757A
JP446428A
JP8149049A
JP6075155A

Attorney, Agent or Firm:

Yosuke Goto (2 outside)

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