Title:
【発明の名称】デュアルポート半導体記憶装置
Document Type and Number:
Japanese Patent JP2871967
Kind Code:
B2
Abstract:
A semiconductor memory device of the present invention is a dual port RAM with write-per-bit function which includes main input buffer circuits and sub input buffer circuits, which take the function of write inhibit detection circuits, and extension bus lines connecting the main and sub input buffer circuits. In the dual port RAM, elements which perform the write inhibit function are not collectively arranged around the data input/output terminals, and, therefore, it is suitable to partitioning of a memory cell array into a plurality of blocks as required due to increase of memory capacity and integration density of the dual port RAM.
Inventors:
NISHIKAWA YASUSHI
Application Number:
JP22110792A
Publication Date:
March 17, 1999
Filing Date:
August 20, 1992
Export Citation:
Assignee:
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
International Classes:
G11C11/401; G06F12/00; G11C7/10; G11C11/4096; (IPC1-7): G06F12/00; G11C11/401
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)