Title:
【発明の名称】プログラム命令語長可変型計算装置及びデータ処理装置
Document Type and Number:
Japanese Patent JP2876773
Kind Code:
B2
Abstract:
A single-packaged central processing unit (CPU) is formed on a substrate for a particular application in a variable word length computer system that includes a program memory. A first semiconductor chip in the CPU is of a general purpose type and includes a plurality of elements interconnected, such as an arithmetic logic unit (ALU), a program counter, and a register. A second semiconductor chip in the CPU is mounted on the first semiconductor chip with their active surfaces facing each other. The second semiconductor chip is configured for the particular application in accordance with a particular program instruction set stored in the program memory. The second semiconductor chip includes a command register for receiving fetched commands from the program memory, a command decoder for decoding the fetched commands and for generating corresponding control signals, and a timing generator for generating system clock signals. In one embodiment, the command register has a particular bit length for adapting to the particular application. In another embodiment, the command decoder has a particular bit length and the timing generator is configured to generate particular corresponding control signals for adapting to the particular application.
Inventors:
TSUKAMOTO TAKASHI
ABE SUKEYUKI
YABUSHITA TETSUO
HAYASHI YOSHIMITSU
ABE SUKEYUKI
YABUSHITA TETSUO
HAYASHI YOSHIMITSU
Application Number:
JP28376290A
Publication Date:
March 31, 1999
Filing Date:
October 22, 1990
Export Citation:
Assignee:
SEIKOO EPUSON KK
International Classes:
G06F9/32; G06F15/78; H01L21/60; H01L23/31; H01L23/492; H01L23/495; H01L23/498; H01L25/065; H01L25/07; H01L25/10; H01L25/18; (IPC1-7): G06F9/32; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP25455A | ||||
| JP6123237A |
Attorney, Agent or Firm:
Minoru Yamada