Title:
【発明の名称】プリフェッチバッファ
Document Type and Number:
Japanese Patent JP2881049
Kind Code:
B2
Abstract:
A prefetch buffer adapted to be installed between a cache memory and a main memory in a computer system having a CPU. The prefetch buffer includes a buffer storage having at least one entry for storing prefetched data and an address tag, which is to be used for searching the data, as a pair; a data searcher for searching, from the data stored in the buffer storage, for data having an address requested by the CPU; and an address estimator for determining an address of data to be prefetched next from the main memory, based on the address requested by the CPU and also on a history of the addresses of data prefetched in the past from the main memory; and an address generator for generating an address of data to be prefetched from the main memory. With this arrangement, it is possible to improve the hit ratio of the prefetch buffer regardless of the direction in which the access address varies.
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Inventors:
MIURA SHUICHI
KUROSAWA KENICHI
NAKAMIGAWA TETSUAKI
HIROSE KENJI
KUROSAWA KENICHI
NAKAMIGAWA TETSUAKI
HIROSE KENJI
Application Number:
JP19024091A
Publication Date:
April 12, 1999
Filing Date:
July 30, 1991
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
HITACHI ENJINIARINGU KK
HITACHI ENJINIARINGU KK
International Classes:
G06F9/38; G06F12/02; G06F12/08; (IPC1-7): G06F9/38; G06F12/08
Domestic Patent References:
| JP1276336A | ||||
| JP63310026A |
Attorney, Agent or Firm:
Kazuko Tomita