Title:
【発明の名称】クランプ機能を有するデータ出力バッファ
Document Type and Number:
Japanese Patent JP2908755
Kind Code:
B2
Abstract:
An integrated circuit data output buffer which may be used in an integrated circuit memory device, includes a data output circuit which is responsive to a data input signal to generate a data output signal, using a boosting data signal. A pulse generator generates a pulse in response to a control signal. A power supply sensing circuit is connected to the pulse generator, and generates a power supply voltage sensing signal in response to the pulse. A clamp circuit is connected to the power supply voltage sensing circuit and to the data output circuit, to clamp the boosting power signal after a predetermined time in response to the power supply voltage sensing signal. Accordingly, output data is buffered by generating a pulse in response to a control signal and generating a power supply voltage sensing signal in response to the pulse. A boosting data signal is clamped after a predetermined time in response to the power supply voltage sensing signal and a data output signal is generated in response to a data input signal, using the clamped boosting data signal. In an integrated circuit memory device, the control signal may be a row address strobe signal.
Inventors:
CHO HORETSU
Application Number:
JP13202096A
Publication Date:
June 21, 1999
Filing Date:
May 27, 1996
Export Citation:
Assignee:
SANSEI DENSHI KK
International Classes:
G11C11/417; G11C7/10; G11C11/409; H03K19/00; H03K19/017; H03K19/0175; (IPC1-7): G11C11/417; G11C11/409; H03K19/0175
Domestic Patent References:
| JP3206717A | ||||
| JP467393A | ||||
| JP537355A | ||||
| JP5291939A |
Attorney, Agent or Firm:
Takeshi Takatsuki