Title:
【発明の名称】エラー検出システム
Document Type and Number:
Japanese Patent JP2919072
Kind Code:
B2
Abstract:
An error detection system for a discrete receiver. Sequences of bits together forming frames of information comprise the signal received by the discrete receiver. The signal is decoded by a convolutional decoder and is re-encoded by an encoder. Successive portions of nonoverlapping sets of adjacently positioned bits of the re-encoded signal formed by the encoder are compared with corresponding bits of a signal representative of the signal received by the receiver. When excessive numbers of the successive portions of the signals which are compared include bit dissimilarities, a bad frame indication is generated.
Inventors:
GUURUDO ADAMU EFU
AROORA AABINDO ESU
AROORA AABINDO ESU
Application Number:
JP51745593A
Publication Date:
July 12, 1999
Filing Date:
March 11, 1993
Export Citation:
Assignee:
MOTOROORA INC
International Classes:
H03M13/23; H03M13/39; H04L1/00; H04L1/20; (IPC1-7): H03M13/12; H04L1/00
Domestic Patent References:
| JPS60177732A | 1985-09-11 | |||
| JPS61135234A | 1986-06-23 | |||
| JPS63142928A | 1988-06-15 | |||
| JPS6490620A | 1989-04-07 | |||
| JPS6490621A | 1989-04-07 |
Attorney, Agent or Firm:
Yoshiaki Ikeuchi