Title:
【発明の名称】メモリアクセス装置
Document Type and Number:
Japanese Patent JP2936036
Kind Code:
B2
Abstract:
An asynchronous access system includes a system bus, at least one processing module provided with a main memory, a central processing unit and a first connection unit which connects to the system bus, and at least one shared memory module provided with a shared memory unit and a second connection unit which connects to the system bus. The first connection unit within the processing module makes a block read request to the shared memory module via the system bus when the first connection unit recognizes a read from the shared memory module requested from the central processing unit. The first connection unit within the processing module comprises an internal bus, an internal buffer storing data read from the shared memory module, a system bus control circuit coupled to the system bus, an internal bus control circuit coupled to the central processing unit via the internal bus, and an internal buffer control circuit controlling write/read of the internal buffer based on a signal from the internal bus control circuit. One of the internal buffer control circuit and the internal bus control circuit invalidates a content of the internal buffer when one of a plurality of invalidating conditions is satisfied.
Inventors:
FUNAKI ATSUSHI
KABEMOTO AKIRA
SUGAWARA HIROHIDE
KABEMOTO AKIRA
SUGAWARA HIROHIDE
Application Number:
JP28868592A
Publication Date:
August 23, 1999
Filing Date:
October 27, 1992
Export Citation:
Assignee:
FUJITSU KK
International Classes:
G06F15/16; G06F12/00; G06F12/08; G06F12/16; G06F13/36; G06F15/177; (IPC1-7): G06F12/00; G06F12/16; G06F15/177
Domestic Patent References:
| JP62298866A |
Attorney, Agent or Firm:
Tadahiko Ito