Title:
【発明の名称】薄膜半導体装置の製造方法
Document Type and Number:
Japanese Patent JP2938121
Kind Code:
B2
Abstract:
In a method of manufacturing a TFT on a transparent insulative substrate 11, a gate electrode 12 is formed selectively on the surface of the substrate 11, and an insulative films 13 and 14, a semiconductor active layer 15 and a channel protection layer 16 are deposited on the entire surface of the resultant structure. Thereafter, the reverse side of the substrate is exposed to pattern the channel protection layer 16, with the gate electrode 12 used as a mask. The reverse side of the substrate is exposed once again, thereby patterning the semiconductor activation layer 15 with the gate electrode 12 used as a mask, such that the width in the channel direction of the semiconductor activation layer 15 is greater than that of the channel protection layer 16. Thus, the semiconductor activation layer 15 and the channel protection layer 16 are formed in a self-alignment manner in relation to the gate electrode 12.
Inventors:
UCHIKOGA SHUICHI
Application Number:
JP8135690A
Publication Date:
August 23, 1999
Filing Date:
March 30, 1990
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
H01L29/78; H01L21/027; H01L21/336; H01L21/77; H01L21/84; H01L29/786; G02F1/1362; (IPC1-7): H01L29/786; H01L21/336
Domestic Patent References:
| JP242761A | ||||
| JP62171160A | ||||
| JP3192731A |
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)